Virage Logic Announces Availability of a Full Suite of 28nm SiWare™ Memory Compilers and Rollout of SiWare™ Logic Libraries for Leading Edge Customers

TSMC Technology Symposium – Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry's trusted IP partner, extends its leadership position by announcing a full suite of 28-nanometer (nm) memory compilers and logic libraries on TSMC’s High-K Metal Gate (28nm HP) process. Following on the early success of their 40nm-node design, two of the company’s longstanding customers have already adopted the 28nm SiWare Memory technology. Virage Logic has had 28nm memory compiler front ends available since December 2009.

Ideal for customers in the graphics, networking, storage, cell phone, and other high performance applications requiring high density and low power, Virage Logic’s SiWare 28nm technology provides a dashboard of options to enable reduced die size, optimal power management, high performance and test and repair options. This capability enables customers to differentiate their products with respect to speed, area, dynamic power, standby power, and cost.

In late 2009, Virage Logic announced its first 28nm test chip tapeouts. Virage Logic’s advanced test chip methodology incorporates at-speed testing through the use of its STAR™ Memory System and STAR™ Silicon Browser tools to measure SRAM bit cell stability, systematic and dynamic variability. This is accomplished with integrated test algorithms that are tailored for advanced processes for higher product reliability and accelerated time-to-yield. These manufacturability enhancements enable customers to minimize their risks at 28nm and accelerate their ramp to volume.

"Building on the company’s proven success of over 20 customers using Virage Logic’s 40nm technology – that includes memory compilers, logic libraries, embedded test and yield optimization solutions, and high speed interface IP – early 28nm technology adopters can reduce their design risk, time-to-market, and the cost of development,” said Brani Buric, executive vice president of marketing and sales for Virage Logic. "With Virage Logic memory and logic already in mass production on 40nm at TSMC, customers can rely on our proven track-record for their 28nm designs.”

"We are pleased to work with Virage Logic in supporting the TSMC 28nm process,” said Shauh-Teh Juang, senior director of design infrastructure marketing for TSMC. "With Virage Logic’s 40nm IP now in mass production, we look forward to another successful collaboration at 28nm in serving our mutual customers to achieve a fast ramp to high volume production.”

"The Virage Logic and TSMC partnership is enabling the industry’s early adopters to proceed with confidence at the advanced process nodes,” noted Rich Wawrzyniak, senior analyst, Semico Research. "Building on the strong momentum this partnership has established on the 40nm node, I’m not surprised that several customers have already selected Virage Logic’s SiWare memories for use on TSMC’s 28nm process.”

Virage Logic’s SiWare Memory supports all major system-on-chip (SoC) power management techniques including Dynamic Voltage Frequency Scaling (DVFS), optional/selectable transistor threshold implants, and multiple standby power management modes that can save 50-90% standby power.

SiWare Memory provides multiple memory architectures for optimal area and speed trade-offs along with advanced integrated and automated instance-based characterization for accuracy. It also offers multiple characterized timing modes to support low voltage operations with high yield, and integrated built-in self-test and repair for at-speed test.

Advanced process nodes such as 40nm and 28nm require advanced characterization methods to properly simulate the effects of process variation. Virage Logic has developed AutoChar^TM, a sophisticated and accurate compiler and instance based characterization system, to dramatically reduce time to develop and deploy memory compilers. This complete software characterization suite is offered to provide customers with the ability to explore a vast array of process, voltage and temperature (PVT) dimensions.

The SiWare Logic libraries include yield-optimized standard cells for a wide variety of design applications with multiple threshold process variants. SiWare Logic libraries are offered in two separate architectures to optimize circuits for High-Speed or High-Density. SiWare Power Optimization Kits provide designers with the most advanced power management capabilities.

About Virage Logic’s SiWare Memory and SiWare Logic Products

The SiWare product line, first introduced in October 2007 for the 65nm process and now in use by more than 20 customers on the 40nm process, has been proven to address the increasingly complex design requirements that are placed on physical IP at advanced processes. The power-optimized memories for advanced processes minimize both static and dynamic power consumption and provide optimal yields. SiWare High-Density memory compilers are optimized to generate memories with minimum area. SiWare High-Speed memory compilers are designed to help designers achieve the most aggressive critical path requirements. Compile-time options for process threshold variants, power saving modes, read and write margin extensions, ultra-low voltage operation, and innovative design for at-speed test enable SoC designers to configure optimal solutions for their specific design requirements.

All SiWare memories are fully supported by Virage Logic's STAR Memory System, the company's flagship embedded memory test and repair system that may be used with Virage Logic memories as well as with other commercially available or internally developed memories. For repair purposes, the STAR Memory System deploys foundry-developed eFuse for repair signature storage. The STAR Memory System employs test algorithms tailored for advanced processes for higher product reliability and accelerated time-to-yield.

The SiWare Logic product line offers yield-optimized High-Speed and High-Density standard cells that are available in multi-channel configurations and multiple threshold variants. These libraries contain over 1,400 base library cells with multiple cell variants and drive strengths to quickly achieve timing closure without wasting area or power. The cells are hand crafted for maximum performance and density.

Virage Logic’s logic libraries maximize yield by adhering to restrictive design rules and multiple contacts for the highest manufacturability and robust electro-migration standards for reliability. Local variations are minimized with uniform layouts, use of non-minimum sized devices, and are accurately characterized in foundry-specified extraction environments that reflect DFM effects such as Well Proximity Effect (WPE) and diffusion spacing with neighboring circuits.

Attendees at the TSMC Symposium will be able to see a live demo showcased by Virage Logic featuring a popular, commercially available, graphics board containing Virage Logic’s 40nm IP that is shipping in high volume.

Availability

Front-end SiWare Memory compilers are available today starting at $130,000 for a single compiler project, which also includes logic libraries, for early adopters of TSMC's 28HP process. Full memory compilers will be available to the general public in June 2010 and logic libraries will be available in Q3 2010.

About Virage Logic

Virage Logic is a leading provider of semiconductor intellectual property (IP) for the design of complex integrated circuits. The company's highly differentiated product portfolio includes processor solutions, interface IP solutions, embedded SRAMs and NVMs, embedded test and yield optimization solutions, logic libraries, and memory development software. As the semiconductor industry's trusted IP partner, more than 400 foundry, IDM and fabless customers rely on Virage Logic to achieve higher performance, lower power, higher density and optimal yield, as well as shorten time-to-market and time-to-volume. For further information, visit http://www.viragelogic.com.

All trademarks are the property of their respective owners and are protected herein.